Device models are commonly used to scientifically model the physical phenomena observed during the operation of semiconductor devices, such as complementary metal oxide semiconductor (CMOS) devices like field effect transistors. Physically-based device modeling for the operational description of semiconductor devices is essential during the design phase to ensure the reliability of integrated circuits containing the semiconductor devices. The device model is an input for a circuit simulator.
When a process for an integrated circuit nears manufacture and before a device model is extracted for manufacture, the predicted device characteristics from the simulations are compared with actual device characteristic derived from measurements executed on a test chip (e.g., a golden chip). The traditional testing process involved characterizing two or more golden chips from among the multiple chips fabricated on a golden wafer for devices of certain widths and lengths from all of the semiconductor devices used in the model library. All device parameters for the device model are extracted using data collected for all devices from a single one of these golden chips, which is chosen as representative of the nominal process conditions for the “process of record”. Ultimately, all device types are modeled from the data collected from this single golden chip.
Because of uncertainties in device manufacturing, it is difficult to produce a single golden chip on a golden wafer that meets all nominal parametric criteria of the fabrication process of record. Spatial variations in the fabrication process give rise to variations among nominally identical devices on different chips at different locations on the golden wafer. Consequently, the location of a chip on the golden wafer may influence the electrical characteristics of a test device of a given width or length.
The general requirement of building a compact device model is that the length and width scaling trends of the semiconductor devices are smooth from the golden chip. As technology scales, the minimum width and length of the semiconductor devices shrink. Consequently, random variations from process factors increase in significance. Eventually, a smooth length-scaling trend and a smooth width-scaling trend from a single golden chip are no longer observed, as apparent from the large variations denoted by the vertical bars visible in FIG. 1. In FIG. 1, curves 10 and 12 representing the saturation threshold voltage of the transistor, Vtsat, as a function of device width is plotted for different test devices on two golden die of a golden wafer, as well as a curve 14 representing the median value of the threshold voltage for the different test devices and vertical bars 16 representing one standard deviation above and below the median value.
To overcome the deficiencies inherent in employing a single golden chip to select parameters for a device model, there is a need for an improved method for selecting parameters for device model extractions.